(preliminary) pl611s-28 1.8v-3.3v picopll tm , world?s smallest programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 3/9/07 page 1 features ? designed for very low-power applications ? offered in tiny green /rohs compliant packages o 6-pin dfn (2.0mmx1.3mmx0.6mm) o 6-pin sc70 (2.3mmx2.25mmx1.0mm) o 6-pin sot23 (3.0mmx3.0mmx1.35mm) ? input frequency: o fundamental crystal: 10mhz to 50mhz o reference input: 1mhz to 200mhz ? accepts >0.1v reference signal input voltage ? output frequency: o < 65mhz @ 1.8v operation o < 90mhz @ 2.5v operation o < 125mhz @ 3.3v operation ? disabled outputs programmable as hiz or active low. ? low current consumption: o <1.2ma @ 27mhz o < 5?a when pdb is activated ? single 1.8v, 2.5v, or 3.3v 10% power supply ? operating temperature range from -40 c to 85 c description the pl611s-28 consumes very low-power while producing high performance clock outputs of up to 55mhz. designed for low-power applications with very stringent space requirement, pl611s-28 consumes about 1.2ma, while producing 2 distinct outputs of 27mhz and 13.5mhz. designed to fit in a small sot, sc70, or sot23 package for high performance applications, the pl611s-28 offers excellent phase noise and jitter performance. the power down feature of pl611s-28, when activated, allows the ic to consume less than 5?a of power, while its programming flexibility allows generating any output, using a low-cost crystal or reference input. in addition, one programmable i/o pin can b e configured as output enable (oe), frequency switching (fsel), power down (pdb) input, or clk1 (f out , f ref , f ref /2) output. package pin configuration block diagram phase detector charge pump loop filter vco xin/fin xout r-counter (8-bit) f vco = f ref * ( 2 * m / r ) f out = f vco / ( 2 * p ) clk0 f ref programming logic oe , fsel, pdb, clk1 xtal osc (11-bit) (5-bit) m-counter p-counter programmable cload programmable function 1 2 3 4 5 6 oe, pdb, fsel, clk1 gnd xin/fin vdd xout clk0 dfn dfn dfn dfn- -- -6 66 6l l l l ( (( (2 22 2. .. .0 00 0mmx mmx mmx mmx1 11 1. .. .3 33 3mmx mmx mmx mmx0 00 0. .. .6 66 6mm mmmm mm) )) ) sot sot sot sot23 2323 23- -- -6 66 6l l l l ( (( (3 33 3. .. .0 00 0mmx mmx mmx mmx3 33 3. .. .0 00 0mmx mmx mmx mmx1 11 1. .. .35 3535 35mm mmmm mm) )) ) 12 3 4 5 6 vdd gnd clk0 sc scsc sc70 7070 70- -- -6 66 6l l l l ( (( (2 22 2. .. .3 33 3mmx mmx mmx mmx2 22 2. .. .25 2525 25mmx mmx mmx mmx1 11 1. .. .0 00 0mm mmmm mm) )) ) xin/fin oe, pdb, fsel, clk1 xin/fin gnd xout vdd clk0 oe , pdb, fsel, clk1 p p p p l l l l 6 6 6 6 1 1 1 1 1 1 1 1 s s s s - - - - 2 2 2 2 8 8 8 8 p p p p l l l l 6 6 6 6 1 1 1 1 1 1 1 1 s s s s - - - - 2 2 2 2 8 8 8 8 12 3 65 4 p p p p l l l l 6 6 6 6 1 1 1 1 1 1 1 1 s s s s - - - - 2 2 2 2 8 8 8 8 xout
(preliminary) pl611s-28 1.8v-3.3v picopll tm , world?s smallest programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 3/9/07 page 2 key programming parameters clk[0:1] output frequency output drive strength programmable input/output f out = f ref * m / (r * p) where m = 11 bit r = 8 bit p = 5 bit clk0 = f out , f ref or f ref / (2*p) clk1 = f ref , f ref /2, clk0 or clk0/2 three optional drive strengths to choose from: ? low: 4ma ? std: 8ma (default) ? high: 16ma one output pin can be configured as: ? oe - input ? pdb - input ? fsel C input ? hiz or active low disabled state package pin assignment pin assignment name sot pin # sc70 pin# dfn pin# type description oe, pdb, fsel, clk1 1 2 2 i/o this programmable i/o pin can be configured as an o utput enable (oe) input, power down (pdb) input, on-the-fly freq uency switching selector (fsel)input or clk1 clock output. this pin has an internal 60kk pull up resistor (oe, pdb & fsel only). the oe and pdb features can be programmed to allow the output to float (hi z), or to operate in the active low mod e. state oe pdb fsel 0 disable clk power down mode frequency 2 1 (default) normal mode normal mode frequency 1 gnd 2 1 3 p gnd connection xin, fin 3 3 1 i crystal or reference input pin crystal output pin xout 4 4 6 o do not connect (dnc ) when fin is present vdd 5 5 5 p vdd connection clk0 6 6 4 o programmable clock output
(preliminary) pl611s-28 1.8v-3.3v picopll tm , world?s smallest programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 3/9/07 page 3 functional description pl611s-28 is a highly featured, very flexible, adva nced programmable pll design for high performance, low- power, small form-factor applications. the pl611s- 28 accepts a fundamental input crystal of 10mhz to 50mhz or reference clock input of 1mhz to 200mhz and is capa ble of producing two outputs up to 125mhz. this fl exible design allows the pl611s-28 to deliver any pll gene rated frequency, f ref (crystal or ref clk) frequency or f ref /(2*p) to clk0 and/or clk1. some of the design fea tures of the pl611s-28 are mentioned below: pll programming the pll in the pl611s-28 is fully programmable. the pll is equipped with an 8-bit input frequency divider (r-counter), and an 11-bit vco frequency feedback loop divider (m-counter). the output of the pll is transferred to a 5-bit post vco divider (p- counter). the output frequency is determined by the following formula [f out = f ref * m / (r * p) ]. clock output (clk0) clk0 is the main clock output. the output of clk0 can be configured as the pll output (f vco /(2*p)), f ref (crystal or ref clk frequency) output, or f ref /(2*p) output. clock output (clk1) the clk1 feature allows the pl611s-28 to have an additional clock output. this output can be programmed to one of the following: f ref - reference (crystal or ref clk) frequency f ref / 2 clk0 clk0 / 2 the output drive level can be programmed to low drive (4ma), standard drive (8ma) or high drive (16ma) for each clock independently. the maximum output frequency is 125mhz. output enable (oe) the output enable feature allows the user to enable and disable the clock output(s) by toggling the oe pin. the oe pin incorporates a 60kk pull up resistor giving a default condition of logic 1. the oe feature can be programmed to allow the output to float (hi z), or to operate in the activ e low mode. power-down control (pdb) the power down (pdb) feature allows the user to put the pl611s-28 into sleep mode. when activated (logic 0), pdb disables the pll, the oscillator circuitry, counters, and all other activ e circuitry. in power down mode the ic consumes <10?a of power. the pdb pin incorporates a 60kk pull up resistor giving a default condition of logi c 1. the pdb feature can be programmed to allow the output to float (hi z), or to operate in the activ e low mode. frequency select (fsel) the frequency select (fsel) feature allows the pl611s-28 to switch between two pre-programmed outputs allowing the device on the fly frequency switching. the fsel pin incorporates a 60kk pull up resistor giving a default condition of logic 1 .
(preliminary) pl611s-28 1.8v-3.3v picopll tm , world?s smallest programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 3/9/07 page 4 electrical specifications absolute maximum ratings parameters symbol min. max. units supply voltage range v dd - 0.5 7 v input voltage range v i - 0.5 v dd + 0.5 v output voltage range v o - 0.5 v dd + 0.5 v soldering temperature (green package) 260 c data retention @ 85 c 10 year storage temperature t s -65 150 c ambient operating temperature* -40 85 c exposure of the device under conditions beyond the limits specified by maximum ratings for extended pe riods may cause permanent damage to the device and affect product reliability. these conditions r epresent a stress rating only, and functional opera tions of the device at these or any other condition s above the operational limits noted in this specification is not implied. *operating temperature is guarante ed by design. parts are tested to commercial grade only. ac specifications parameters conditions min. typ. max. units crystal input frequency (xin) fundamental crystal 1 0 50 mhz @ v dd =3.3v 200 @ v dd =2.5v 166 input (fin) frequency @ v dd =1.8v 133 mhz input (fin) signal amplitude internally ac coupled (high frequency) 0.9 v dd vpp input (fin) signal amplitude internally ac coupled (low frequency) 3.3v < 50mhz, 2.5v < 40mhz, 1.8v < 15mhz 0.1 v dd v pp @ v dd =3.3v 125 mhz @ v dd =2.5v 90 mhz output frequency @ v dd =1.8v 65 mhz settling time at power-up (after v dd increases over 1.62v) 2 ms oe function; ta=25o c, 15pf load 10 ns output enable time pdb function; ta=25o c, 15pf load 2 ms vdd sensitivity frequency vs. v dd +/-10% -2 2 ppm output rise time 15pf load, 10/90% v dd , high drive, 3.3v 1.2 1.7 ns output fall time 15pf load, 90/10% v dd , high drive, 3.3v 1.2 1.7 ns duty cycle v dd /2 45 50 55 % period jitter,pk-to-pk* (measured from 10,000 samples) with capacitive decoupling between v dd and gnd. 70 ps * note: jitter performance depends on the programmi ng parameters.
(preliminary) pl611s-28 1.8v-3.3v picopll tm , world?s smallest programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 3/9/07 page 5 dc specifications parameters symbol conditions min. typ. max. units supply current, dynamic, with loaded cmos outputs i dd @ v dd =3.3v, 27mhz, load=15pf 4.0 ma supply current, dynamic, with loaded cmos outputs i dd @ v dd =2.5v, 27mhz, load=10pf 2.7 ma supply current, dynamic with loaded cmos outputs i dd @ v dd =1.8v, 27mhz, load=5pf 1.2 ma pll off: supply current, dynamic, with loaded cmos output i dd @ v dd =3.3v, 27mhz, load=15pf 2.0 ma pll off: supply current, dynamic, with loaded cmos output i dd @ v dd =2.5v, 27mhz, load=10pf 1.3 ma pll off: supply current, dynamic with loaded cmos output i dd @ v dd =1.8v, 27mhz, load=5pf 0.8 ma supply current, dynamic, with loaded outputs i dd when pdb=0 5 ?a operating voltage v dd 1.62 3.63 v output low voltage v ol i ol = +4ma standard drive 0.4 v output high voltage v oh i oh = -4ma standard drive v dd C 0.4 v output current, low drive i osd v ol = 0.4v, v oh = 2.4v 4 ma output current, standard drive i osd v ol = 0.4v, v oh = 2.4v 8 ma output current, high drive i ohd v ol = 0.4v, v oh = 2.4v 16 ma * note: please contact phaselink, if super-low-powe r is required. crystal specifications parameters symbol min. typ. max. units fundamental crystal resonator frequency f xin 10 50 mhz crystal loading rating (the ic can be programmed for any value in this ran ge.) c l (xtal) 8 12 pf maximum sustainable drive level 100 w operating drive level 30 w shunt capacitance c0 5.5 pf metal can crystal esr max esr 50 k shunt capacitance c0 2.5 pf small smd crystal esr max esr 80 k
(preliminary) pl611s-28 1.8v-3.3v picopll tm , world?s smallest programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 3/9/07 page 6 layout recommendations dfn-6l evaluation board the following guidelines are to assist you with a p erformance optimized pcb design: signal integrity and termination considerations - keep traces short! - trace = inductor. with a capacitive load this eq uals ringing! - long trace = transmission line. without proper termination this will cause reflections ( looks lik e ringing ). - design long traces as ?striplines? or ?microstrip s? with defined impedance. - match trace at one side to avoid reflections bouncing back and forth. decoupling and power supply considerations - place decoupling capacitors as close as possible to the vdd pin(s) to limit noise from the power supply - multiple vdd pins should be decoupled separately for best performance. - addition of a ferrite bead in series with vdd can help prevent noise from other board sources - value of decoupling capacitor is frequency dependant. typical values to use are 0.1 f for designs using crystals < 50mhz and 0.01 f for designs using crystals > 50mhz. typical cmos termination place series resistor as close as possible to cmos output cmos output buffer ( typical buffer impedance 20 to cmos input series resistor use value to match output buffer impedance to 50 trace. typical value 30 50 line
(preliminary) pl611s-28 1.8v-3.3v picopll tm , world?s smallest programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 3/9/07 page 7
(preliminary) pl611s-28 1.8v-3.3v picopll tm , world?s smallest programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 3/9/07 page 8 d e pin1 dot d1 b e e1 l a3 a a1 pin 6 id chamfer package drawings ( green package compliant) sot23-6l sc70-6l dfn-6l dimension in mm symbol min. max. a 1.05 1.35 a1 0.05 0.15 a2 1.00 1.20 b 0.30 0.50 c 0.08 0.20 d 2.80 3.00 e 1.50 1.70 h 2.60 3.00 l 0.35 0.55 e 0.95 bsc dimension in mm symbol min. max. a 0.80 1.00 a1 0.00 0.09 a2 0.80 0.91 b 0.15 0.30 c 0.08 0.25 d 1.85 2.25 e 1.15 1.35 h 2.00 2.30 l 0.21 0.41 e 0.65bsc dimension in mm symbol min. max. a 0.50 0.60 a1 0.00 0.05 a3 0.152 0.152 b 0.15 0.25 e 0.40bsc d 1.25 1.35 e 1.95 2.05 d1 0.75 0.85 e1 0.95 1.05 l 0.20 0.30 c l a2 e h d a1 e b a pin1 dot c l a2 e h d a1 e b a pin1 dot
(preliminary) pl611s-28 1.8v-3.3v picopll tm , world?s smallest programmable clock 47745 fremont blvd., fremont, california 94538 tel (510) 492-0990 fax (510) 492-0991 www.phaselink.com rev 3/9/07 page 9 ordering information ( green package) for part ordering, please contact our sales department: 47745 fremont blvd., fremont, ca 94538, usa tel: (510) 492-0990 fax: (510) 492-0991 part number the order number for this device is a combination o f the following: part number, package type and operating temperature range pl611 s-28-xxx x x x part/order number marking ? package option pl611s-28-xxxgc-r xxx 6-pin dfn (tape and reel) pl611s-28-xxxuc-r xxx 6-pin sc70 (tape and reel) pl611s-28-xxxtc-r 28xxx 6-pin sot23 (tape and reel) ? note: xxx designates marking identifier that, at times, could be independent of the part number. pl ease consult your phaselink sales f or marking information. phaselink corporation, reserves the right to make c hanges in its products or specifications, or both a t any time without notice. the information furnished by phaselink is believed to be accurate a nd reliable. however, phaselink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any lo ss or damage of whatever nature resulting from the use of, or reliance upon this product. life support policy : phaselinks products are not authorized for use a s critical components in life support devices or sy stems without the express written approval of the president of phasel ink corporation. solder reflow profile available at www.phaselink.com/qa/solderinggreen.pdf part number temperature c=commercial i = industrial package type g=dfn-6l u=sc70-6l t=sot23-6l 3 digit id code * (will be assigned at programming time) n one= tube r=tape and reel
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